(1) Field of the Invention
The present invention relates to processes used to fabricate metal oxide semiconductor field effect transistor, (MOSFET), devices, and more specifically to a process used to create a gate structure for a MOSFET device.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase the performance of semiconductor devices. The ability to create semiconductor devices with sub-micron features, or micro-miniaturization, has allowed this performance objective to be successfully addressed. The use of sub-micron features has resulted in a reduction in performance degrading capacitances and resistances, present with larger dimension, semiconductor devices. Advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching, have contributed to micro-miniaturization of advanced semiconductor devices. For example the use of more advanced exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be successfully formed in photoresist layers. In addition the development of more sophisticated dry etching tools and processes, have in turn allowed the sub-micron features, in masking photoresist layers, to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices.
An area, critical for the performance of semiconductor MOSFET devices, is the channel region, or the region of the MOSFET device, located underlying a gate structure, between source and drain regions. The MOSFET source and drain regions are formed self-aligned, to an overlying gate structure, therefore the channel length of the MOSFET device is directly related to the width of the overlying gate structure. The advances in photolithography and dry etching disciplines have allowed gate structures, exhibiting sub-micron widths, to be routinely achieved, therefore resulting in the desired channel lengths, and thus satisfying desired performance objectives. However specific semiconductor process phenomena can interfere with the attainment of the minimum channel lengths offered by the narrow gate width, achieved via advanced photolithographic and dry etching procedures. For example, prior to the creation of a lightly doped source and drain, (LDD), region, self-aligned to a gate structure, a thermal oxidation procedure is performed to protect the sides of the gate structure from the subsequent ion implantation procedure, used to create the LDD region. The gate structure can be a polycide structure, comprised of a metal silicide layer, such as tungsten silicide, overlying a polysilicon layer. The oxidation procedure can create protrusions extending from the exposed sides of the metal silicide component of the polycide gate structure, increasing the width of the gate structure. However of greater concern is the enhanced oxidation rate of the metal silicide component, in relation to the underlying polysilicon component, of the polycide gate structure, resulting in a thicker than desired insulator layer, on the exposed sides of the metal silicide component. This unwanted feature, thicker than desired oxide on the side of the metal silicide, results in an increase in channel length due to the inability of the LDD ion implantation procedure, to self-align to the dimension that the gate structure was designed to.
This invention will describe a process of creating a polycide gate structure, in which a subsequent protective oxide layer, formed on the sides of the polycide gate structure, does not adversely influence the narrow polycide gate width dimension, and thus not adversely influence the channel length of the MOSFET device. This is achieved via a novel dry etching procedure, incorporating anisotropic, as well as isotropic etch cycles, used to form a polycide gate structure exhibiting a shape that will accept the formation of insulator growth, on the exposed sides of the metal silicide component, however without an increases in polycide gate width. Prior art, such as Park, et cl, in U.S. Pat. No. 5,545,578, describe a method for forming a specific polycide shape, used to prevent subsequent oxidation of the exposed polycide sidewall. In contrast this present invention describes the formation of unique polycide shape, which allows subsequent oxidation of the exposed sides to occur, however allowing the unique polycide shape to compensate for the oxidation formation.